1. Field of the Disclosure
The present invention relates to a thin film transistor substrate having a self-alignment function to reduce production cost accordingly and a method of fabricating the thin film transistor, and a flat display having the thin film transistor substrate.
2. Discussion of the Related Art
In recent, a display device market has been changing rapidly, focused on flat display devices efficient to apply an enlarge size and a compact size to. Such a flat display device may be classified into a liquid crystal display (LCD), a plasma display panel (PDP), an organic electro luminescence display (OLED) and the like. The flat display device uses a glass substrate as supporting body configured to support a plurality of fin films. The glass substrate has limitation of lessened thickness. Even if the thickness of the glass substrate is lessened, the glass substrate has a disadvantage of easily-breakable because it has no durability and flexibility.
As a result, flexible displays have been emerging in the market which uses material having a thin thickness and durability, for example, plastic instead of glass substrate having no durability and flexibility.
Compared with the glass substrate, it is easy to change a shape of a plastic film used in such a flexible display because of heat, tension, chemical reaction and moisture absorption and the like. Because of that, an exterior appearance of the flexible substrate has to be put into consideration in each assembly line disadvantageously. Especially, the plastic film happens to be thermal-contractible by 200 ppm at 150° C. If a flexible display is fabricated, using such the plastic film, accuracy of thin-film-inter-layer alignment would deteriorate seriously.
To solve this problem, U.S. Pat. No. 7,202,179 and U.S. Pat. No. 7,521,313 disclose a thin film device having self aligned imprint lithography.
Specifically, according to U.S. Pat. No. 7,202,179, a plurality thin film device layers are deposited on a substrate and an imprinted 3D template structure, such as an imprinted polymer, is then provided on the plurality of thin film device layers. After that, the plurality of thin film device layers and the 3D template structure are etched. This etching forms a rudimentary structure for a thin film device. That is, the formed plurality of thin film device layers is patterned by using multi-stepped resist as mask through a plurality of asking and etching processes. In this case, a problem of multi-layer alignment may be solved because the multi-stepped resist is used in patterning the plurality of thin film device layers. However, undercutting is used to pattern a gate layer which is the lowest layer. Here, it is difficult to perform an undercut process and there is limitation of forming a pattern shape. Also, a gate dielectric layer provided on the gate layer might be floating because of the undercut structure and product reliability would deteriorate accordingly.
According to U.S. Pat. No. 7,512,313, when forming a pattern in an exposed area of a substrate having at least one step, exposed area is treated to provide at least one etch resist area of material. However, the material the surface treating process is applied to is limited and it is difficult to secure that kind of material. Also, the surface treating process is additionally provided and the overall assembly process has to be complicated accordingly.